ADI 公司的ADRF6655是集成了PLL和VCO的高动态范围的有源混频器, 输入频率范围100MHz - 2500 MHz,内部LO频率范围从1050 MHz 到2300 MHz,输入P1dB为12dBm,输入IP3为29dBm,噪音(SSB)为12dB,电压转换增益6dB,200欧姆输出匹配阻抗. ADRF6655主要用在宽带通信设备如点对点微波通信,无线基站,国防宽带和软件定义无线电(SDR),蜂窝中继器以及通信测试设备.本文介绍ADRF6655主要特性, 功能方框图, PLL和VCO方框图,以及850MHz, 900MHz, 1200MHz, 1300MHz, 1600MHz和2100MHz输出匹配网络,评估板电路图和评估板配置元件表.
The ADRF6655 is a high dynamic range active mixer with integrated PLL and VCO. The synthesizer uses a programmable integer-N/fractional-N PLL to generate a local oscillator input to the mixer. The PLL reference input is nominally 20 MHz. The reference input can be divided by or multiplied by and then applied to the PLL phase detector. The PLL can support input reference frequencies from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The VCO output at 2 × fLO is then applied to a local oscillator (LO) divider as well as to a programmable PLL divider. The programmable divider is controlled by an Σ-Δ modulator (SDM). The modulus of the SDM can be programmed between 1 and 2047.
The broadband, active mixer employs a bias adjustment to allow for enhanced IP3 performance at the expense of increased supply current. The mixer provides an input IP3 exceeding 25 dBm with 12 dB single sideband NF under typical conditions. The IIP3 can be boosted to ~29 dBm with roughly 20 mA of additional supplied current. The mixer provides a typical voltage conversion gain of 6 dB with a 200 Ω differential IF output impedance. The IF output can be externally matched to support upconversion over a limited frequency range.
The ADRF6655 is fabricated using an advanced silicon-germanium BiCMOS process. It is packaged in a 40-lead, exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a −40℃ to +85℃ temperature range.
ADRF6655主要特性:
Broadband active mixer with integrated fractional-N PLL
RF input frequency range: 100 MHz to 2500 MHz
Internal LO frequency range: 1050 MHz to 2300 MHz
Flexible IF output interface
Input P1dB: 12 dBm
Input IP3: 29 dBm
Noise figure (SSB): 12 dB
Voltage conversion gain: 6 dB
Matched 200 Ω output impedance
SPI serial interface for PLL programming
40-lead 6 mm × 6 mm LFCSP
图1. ADRF6655功能方框图
图2. ADRF6655 PLL和VCO方框图
图3. ADRF6655混频器方框图
图4. ADRF6655 850MHz输出匹配网络图(800MHz-925MHz输出回波损耗大于12dB)
图5. ADRF6655 900MHz输出匹配网络图(815MHz-1075MHz输出回波损耗大于12dB)
图6. ADRF6655 1200MHz输出匹配网络图(950MHz-1500MHz输出回波损耗大于12dB)
图7. ADRF6655 1300MHz输出匹配网络图(1075MHz-1525MHz输出回波损耗大于12dB)
图8. ADRF6655 1600MHz输出匹配网络图(140MHz-1680MHz输出回波损耗大于12dB)
图9. ADRF6655 2100MHz输出匹配网络图(2000MHz-2200MHz输出回波损耗大于12dB)
图10. ADRF6655评估板电路图
ADRF6655评估板配置元件表:
详情请见:
http://www.analog.com/static/imported-files/data_sheets/ADRF6655.pdf
The ADRF6655 is a high dynamic range active mixer with integrated PLL and VCO. The synthesizer uses a programmable integer-N/fractional-N PLL to generate a local oscillator input to the mixer. The PLL reference input is nominally 20 MHz. The reference input can be divided by or multiplied by and then applied to the PLL phase detector. The PLL can support input reference frequencies from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The VCO output at 2 × fLO is then applied to a local oscillator (LO) divider as well as to a programmable PLL divider. The programmable divider is controlled by an Σ-Δ modulator (SDM). The modulus of the SDM can be programmed between 1 and 2047.
The broadband, active mixer employs a bias adjustment to allow for enhanced IP3 performance at the expense of increased supply current. The mixer provides an input IP3 exceeding 25 dBm with 12 dB single sideband NF under typical conditions. The IIP3 can be boosted to ~29 dBm with roughly 20 mA of additional supplied current. The mixer provides a typical voltage conversion gain of 6 dB with a 200 Ω differential IF output impedance. The IF output can be externally matched to support upconversion over a limited frequency range.
The ADRF6655 is fabricated using an advanced silicon-germanium BiCMOS process. It is packaged in a 40-lead, exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a −40℃ to +85℃ temperature range.
ADRF6655主要特性:
Broadband active mixer with integrated fractional-N PLL
RF input frequency range: 100 MHz to 2500 MHz
Internal LO frequency range: 1050 MHz to 2300 MHz
Flexible IF output interface
Input P1dB: 12 dBm
Input IP3: 29 dBm
Noise figure (SSB): 12 dB
Voltage conversion gain: 6 dB
Matched 200 Ω output impedance
SPI serial interface for PLL programming
40-lead 6 mm × 6 mm LFCSP
图1. ADRF6655功能方框图
图2. ADRF6655 PLL和VCO方框图
图3. ADRF6655混频器方框图
图4. ADRF6655 850MHz输出匹配网络图(800MHz-925MHz输出回波损耗大于12dB)
图5. ADRF6655 900MHz输出匹配网络图(815MHz-1075MHz输出回波损耗大于12dB)
图6. ADRF6655 1200MHz输出匹配网络图(950MHz-1500MHz输出回波损耗大于12dB)
图7. ADRF6655 1300MHz输出匹配网络图(1075MHz-1525MHz输出回波损耗大于12dB)
图8. ADRF6655 1600MHz输出匹配网络图(140MHz-1680MHz输出回波损耗大于12dB)
图9. ADRF6655 2100MHz输出匹配网络图(2000MHz-2200MHz输出回波损耗大于12dB)
图10. ADRF6655评估板电路图
ADRF6655评估板配置元件表:
详情请见:
http://www.analog.com/static/imported-files/data_sheets/ADRF6655.pdf
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