芯片电感器：有助催生新一代微型射频电子与无线通讯系统设计

美国加州大学柏克莱分校 （UCBerkeley）的科学家们表示已经找到一种可推动芯片电感器 （on-chipinductor）技术进展的新方法，将有助于催生新一代微型射频 （RF）电子与无线通讯系统设计。

加州大学的研究人员们深入探索在纳米磁铁 （nanomagnet）中纳米材料合成的最新发展。根据加州大学柏克莱分校机械工程系教授Liwei Lin表示，研究人员们发现，采用外覆绝缘层的磁性纳米粒子可使高频的芯片电感器尺寸缩小，同时提升性能，同时，通过其高截止频率提供良好的导磁率，从而降低在高频作业时的涡流损耗。

工程师们经常面对的问题是，在试图缩减芯片电感器尺寸的同时，还得保持其最佳电感与性能。Liwei Lin表示这些困难主要来自于“基本科学以及工程实践约束”所造成的限制。

芯片电感器技术并未发生像电晶体技术一样的进展电晶体技术在过去40年来一直遵循摩尔定律。电感器在电路上算是一款被动元件被归类于“超越摩尔定律”的领域，因此整合的是不会因摩尔定律而微缩的RF与MEMS等非数位化功能。

芯片电感器架构需要较大的面积，因为在其金属走线之间需要一定的长度、匝数、厚度与空间，以实现适当的电感与性能。然而，对于要求较大的面积则可能会因为在旋转线圈和半导体基板之间产生寄生效应而造成电感损失。

因此，电感器在微型化时必须添加磁性材料，但在这方面也带来其他的技术限制，例如制程方案、相容于标准制程，以及材料的稳定度，Liwei Lin说，磁性材料在磁导率和频率响应方面存在一些限制。

新的电感器制造技术采用绝缘的纳米复合磁性物质作为填充材料来减少芯片电感器尺寸，以及提高达80%的电感，从而使芯片电感器缩减至少50%。此外，LiweiLin强调，它还具有使作业频率范围从GHz级扩展至10GHz的潜力。

他预计电感器技术的这些进展可望在未来3-5年内落实应用于芯片制程中。

原文参考：

UC Berkeley Scientists Advance On-Chip Inductor Technology

by:eetimes

University of California Berkeley scientists say they have found a way to advance on-chip inductor technology, triggering a new generation of miniature RF electronics and wireless communications systems.

The UC research delved into recent developments in nanomaterial synthesis of nanomagnets. Liwei Lin, a professor of mechanical engineering at UC Berkeley, told us the researchers found that using magnetic nanoparticles with a coating of insulators shrinks the size and improves the performance of high-frequency on-chip inductors. "They provide good magnetic permeability with high cutoff frequency while reducing the eddy current losses at high-frequency operations."

Engineers have had problems trying to reduce the size of on-chip inductors while maintaining optimum levels of inductance and performance. Difficulties stem from limitations set by "fundamental sciences and constraints set by engineering practice," Lin said.

On-chip inductor technology hasn't progressed the same way as transistor technology, which has followed Moore's Law over the past 40 years. Inductors -- technically passive elements in circuitry -- fall into the "More Than Moore" domain, in which devices integrate nondigital functions such as RF and MEMS that do not scale to Moore's Law.

When on-chip inductors are constructed, large areas are required, because they need a certain length, number of turns, thickness, and space between metal traces to achieve adequate levels of inductance and performance. However, the large area requirements produce inductance losses because of the parasitic effects between the spiral coil and the semiconductor substrate.

As a result, miniaturization will require the addition of magnetic materials, but they have their own technical limitations, "such as processing schemes, compatibility with standard processes, and material stabilities," Lin said. "Magnetic materials have fundamental limits on their permeability and frequency responses."

The new inductor fabrication technology, which uses insulated nano-composite magnetic materials as the filling material to reduce the size of the on-chip inductors, enhances inductance by up to 80%, resulting in at least 50% shrinkage in the on-chip inductor. It also has the potential to extend the operational frequency range from the GHz range to the 10-GHz range, Lin said.

He expects these advancements to be applied to the chip manufacturing process in 3-5 years.

The UC Berkeley research has been sponsored by Semiconductor Research Corp., the university research consortium for semiconductors and related technologies in Research Triangle Park, N.C.